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82008mspc 20080710-s00008 no.a1271-1/21 http://onsemi.com semiconductor components industries, llc, 2013 july, 2013 ordering information see detailed ordering and shipping informat ion on page 21 of this data sheet. lv8105w overview the lv8105w is a predriver ic designed for variable speed control of 3-phase brushless motors. it can be used to implement a high- and low-side output n-channel power fet drive circuit using a built-in charge pump circuit. high-efficiency drive is possible through the use of low noise pwm drive and synchronous rectifying systems. functions ? speed discriminator and pll speed control system ? built-in vco circuit for generating th e speed discriminator reference signal ? speed lock detection output ? hall bias switch ? braking circuit (short braking) ? full complement of on-chip protection circuits, including current limiter and lock protection circuits. specifications absolute maximum ratings at ta = 25 ? c parameter symbol conditions ratings unit supply voltage v cc max v cc = vg 42 v charge pump output voltage vg max vg pin 42 v output current i o max1 pins ul, vl, wl -15 to 15 ma i o max2 pins uh, vh, wh, uout, vout and wout -20 to 20 ma allowable power dissipation pd max1 independent ic 0.45 w pd max2 mounted on the specified board * 1.30 w operating temperature topr -20 to +80 ? c storage temperature tstg -55 to +150 ? c * specified board:114.3mm 76.1mm 1.6mm, glass epoxy board. bi-cmos ic three-phase brushless motor predriver for variable speed control orderin g numbe r : ena1271 sqfp48(7x7) stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should n ot be assumed, damage may occur and reliability may be affected.
lv8105w no.a1271-2/21 allowable operating range at ta = 25 ? c parameter symbol conditions ratings unit supply voltage range v cc 16 to 28 v 5v constant voltage output current i reg 0 to -10 ma hb pin output current i hb 0 to -25 ma ld pin applied voltage v ld 0 to 6 v ld pin output current i ld 0 to 5 ma fgs pin applied voltage v fgs 0 to 6 v fgs pin output current i fgs 0 to 5 ma electrical characteristics at ta ? 25 ? c, v cc = 24v parameter symbol conditions ratings unit min typ max supply current 1 i cc 1 7 8.8 ma supply current 2 i cc 2 at stop 3 3.8 ma 5v constant-voltage output (vreg pin) output voltage vreg i o = 5ma 5.2 5.6 6.0 v line regulation ? v (reg1) v cc = 16 to 28v 10 50 mv load regulation ? v (reg2) i o = -5 to -10ma 10 50 mv output block / conditions : apply a vg voltage of 33v high level output voltage 1 v oh 1 pins ul, vl and wl i oh = -2ma vreg-0.65 vreg-0.5 vreg-0.35 v low level output voltage 1 v ol 1 pins ul, vl and wl i ol = 2ma 0.35 0.5 0.65 v high level output voltage 2 v oh 2 pins uh, vh and wh i oh = -2ma vg-0.65 vg-0.5 vg-0.35 v low level output voltage 2 v ol 2 pins uh, vh and wh i ol = 2ma 0.45 0.6 0.8 v pwm frequency f (pwm) 51 64 77 khz internal oscillator oscillation frequency f (r ef) 1.65 2.05 2.45 mhz charge pump output (vg pin) output voltage vgout v cc +8.0 v cc +9.0 v cc +10.0 v cp1 pin high level output voltage v oh (cp1) icp1 = -2ma v cc -1.35 v cc -1.0 v cc -0.7 v low level output voltage v ol (cp1) icp1 = 2ma 0.5 0.65 0.8 v charge pump frequency f (cp1) 102 128 154 khz hall amplifier input bias current ihb (ha) -2 -0.1 ? a common-mode input voltage range 1 vicm1 when using hall elements 0.3 3.5 v common-mode input voltage range 2 vicm2 at one-si de input bias (hall ic application) 0 vreg v hall input sensitivity sin wave 50 mvp-p hysteresis width ? v in (ha) 5 13 24 mv input voltage low ? high vslh 2 7 12 mv input voltage high ? low vshl -12 -6 -2 mv hb pin output voltage vhbo ihb = -15ma v cc -0.8 v cc -0.5 v cc -0.35 v output leakage current il (hb) v o = 0v -10 ? a fg amplifier input offset voltage v io (fg) -10 10 mv input bias current ib (fg) -1 1 ? a reference voltage vb (fg) -5% vreg/2 5% v high level output voltage v oh (fg) ifgi = -0.1ma, no load 3.95 4.4 4.85 v low level output voltage v ol (fg) ifgi = 0.1ma, no load 0.75 1.2 1.65 v fg input sensitivity gain : 100 times 3 mv schmitt width of the next stage one-side hysteresis comparator 120 200 280 mv operation frequency range 3 khz open-loop gain f fg = 2khz 45 48 db continued on next page. functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recomme nded operating ranges limits may affect device r eliab ility.
lv8105w no.a1271-3/21 continued from preceding page. parameter symbol conditions ratings unit min typ max fgs output output saturation voltage v ol (fgs) i fgs = 2ma 0.2 0.4 v output leakage current il (fgs) v o = 6v 10 ? a csd oscillator high level output voltage v oh (csd) 2.9 3.4 3.9 v low level output voltage v ol (csd) 1.6 2.0 2.4 v amplitude v (csd) 1.15 1.4 1.65 vp-p external capacitor charge current ichg1 -13 -10 -7 ? a external capacitor discharge current ichg2 7.5 10.5 13.5 ? a oscillation frequency f (csd) c = 0.047 ? f 78 hz speed discriminator output high level output voltage 1 v oh 1 (d) vreg-1.25 vreg-1.0 vreg-0.75 v low level output voltage 1 v ol 1 (d) 0.65 0.9 1.15 v high level output voltage 2 v oh 2 (d) vreg-2.0 vreg-1.7 vreg-1.4 v low level output voltage 2 v ol 2 (d) 1.3 1.6 1.9 v counts 512 ld output output saturation voltage v ol (ld) ild = 2ma 0.2 0.4 v output leakage current il (ld) v o = 6v 10 ? a lock range -6.25 +6.25 % speed control pll output high level output voltage v oh (p) vreg-2.0 vreg-1.7 vreg-1.4 v low level output voltage v ol (p) 1.3 1.6 1.9 v current control circuit drive gain gdf 0.20 0.25 0.32 current limiter operation limiter voltage vrf 0.23 0.25 0.275 v integrator input offset voltage v io (int) -10 10 mv input bias current ib (int) -1 1 ? a reference voltage vb (int) -5% vreg/2 5% v high level output voltage v oh (int) i int i = -0.1ma, no load 3.95 4.4 4.85 v low level output voltage v ol (int) i int i = 0.1ma, no load 0.75 1.2 1.65 v open-loop gain f int = 2khz 45 48 db vco oscillator (c pin) oscillation frequency range f (c) c = 120pf, r = 24k ? 0.15 1.54 mhz high level output voltage v oh (c) fil = 2.5v 2.71 3.16 3.61 v low level output voltage v ol (c) fil = 2.5v 2.20 2.60 3.00 v amplitude v (c) fil = 2. 5v 0.44 0.56 0.68 vp-p fil pin output source current i oh (fil) -15 -11 -6 ? a output sink current i ol (fil) 6 10 15 ? a rc pin comparator voltage vrc vreg ? 0.59 vreg ? 0.60 vreg ? 0.61 v low-voltage protection circuit operation voltage vlvsd 8.00 8.54 9.00 v hysteresis width ? vlvsd 0.25 0.34 0.45 v thermal shutdown operation thermal shutdown operation temperature tsd design target value* 150 175 ? c hysteresis width ? tsd design target value* 30 ? c note : * these items are design target values and are not tested. continued on next page.
lv8105w no.a1271-4/21 continued from preceding page. parameter symbol conditions ratings unit min typ max clk pin input frequency fi (clk) 3 khz high level input voltage range v ih (clk) 2.0 vreg v low level input voltage range v il (clk) 0 1.0 v input open voltage v io (clk) vreg-0.5 vreg v hysteresis width v is (clk) design target value* 0.18 0.27 0.36 v high level input current i ih (clk) vclk = 5v -22 -10 -3 ? a low level input current i il (clk) vclk = 0v -133 -93 -70 ? a pull-up resistance ru (clk) 45 60 75 k ? s/s pin high level input voltage range v ih (s/s) 2.0 vreg v low level input voltage range v il (s/s) 0 1.0 v input open voltage v io (s/s) vreg-0.5 vreg v hysteresis width v is (s/s) 0.18 0.27 0.36 v high level input current i ih (s/s) vs/s = 5v -22 -10 -3 ? a low level input current i il (s/s) vs/s = 0v -133 -93 -70 ? a pull-up resistance ru (s/s) 45 60 75 k ? f/r pin high level input voltage range v ih (f/r) 2.0 vreg v low level input voltage range v il (f/r) 0 1.0 v input open voltage v io (f/r) vreg-0.5 vreg v hysteresis width v is (f/r) 0.18 0.27 0.36 v high level input current i ih (f/r) vf/r = 5v -22 -10 -3 ? a low level input current i il (f/r) vf/r = 0v -133 -93 -70 ? a pull-up resistance ru (f/r) 45 60 75 k ? br pin high level input voltage range v ih (br) 2.0 vreg v low level input voltage range v il (br) 0 1.0 v input open voltage v io (br) vreg-0.5 vreg v hysteresis width v is (br) 0.18 0.27 0.36 v high level input current i ih (br) vbr = 5v -22 -10 -3 ? a low level input current i il (br) vbr = 0v -133 -93 -70 ? a pull-up resistance ru (br) 45 60 75 k ? note : * these items are design target values and are not tested. product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product per formance may not be indicated by the electrical characteristics if operated under different conditions.
lv8105w no.a1271-5/21 package dimensions unit : mm (typ) sqfp48(7x7) pin assignment pd max ? ta 0 1.0 1.3 0.5 0.45 1.5 ? 20 80 0.73 0.25 60 20 40 0 100 independent ic ambient temperature, ta ? c allowable power dissipation, pd max ? w specified board : 114.3 76.1 1.6mm 3 glass epoxy mounted on a board 1 37 38 39 40 41 42 43 44 45 46 47 48 lv8105 csd 2 nc 3 rc 4 intout 5 intin 6 intref 7 dout 8 pout 9 s/s 10 clk 11 f/r 12 br 36 wh 35 wout 34 wl 33 vh 32 vout 31 vl 30 uh 29 uout 28 ul 27 nc 26 rf 25 rfgnd nc v cc vg cp2 cp1 nc vreg gnd2 gnd1 c r fil 24 23 22 21 20 19 18 17 16 15 14 13 hb in3 + in3 - in2 + in2 - in1 + in1 - fgin + fgin - fgout ld fgs 7.0 7.0 9.0 9.0 0.15 0.5 (1.5) 0.1 1.7max 0.18 0.5 (0.75) 112 13 24 25 36 37 48
lv8105w no.a1271-6/21 three-phase logic truth table (a high level input is the state where in + > in - .) f/r = ?l? f/r = ?h? drive output in1 in2 in3 in1 in2 in3 upper gate lower gate 1 h l h l h l vh ul 2 h l l l h h wh ul 3 h h l l l h wh vl 4 l h l h l h uh vl 5 l h h h l l uh wl 6 l l h h h l vh wl when f/r is ?l?, the hall input while the motor is rotating must be input in order from 1 to 6 of the above table. when the hall input is performed by the reverse order, it will not become the soft current-carrying output. (the motor is driven by the 12 0 degrees current-carrying only.) also, when f/r is ?h?, the hall input while the motor is rotating must be input in order from 6 to 1 of the above table. when the hall input is performed by the reverse order, it will not become the soft current-carrying output. (the motor is driven by the 12 0 degrees current-carrying only.) s/s input br input input mode input mode high or open stop high or open brake low start low release current control characteristics rf ? intout (typical characteristics) 0 0.2 0.25 0.1 0.3 1.5 3.5 2.5 3.0 3.2 2.0 2.2 4.0 intout ? v rf?v gain = 0.25
lv8105w no.a1271-7/21 block diagram (referance constants) + fgs dout fgout r c fil clk fgin - fgin + vreg vreg vreg int out int in int ref 24v v cc hb hb hall hys comp hall fil frequency multiply in3 + in3 - in2 + in2 - in1 + dout pout in1 - rc csd br rf gnd2 gnd1 f/r rfgnd s/s vreg pre driver drive logic + - + - 47 f 0.1 f 0.1 f 0.1 f 62 vh 62 vout 100 0.01 f 180pf 180pf 680pf 0.1 f 0.068 f 0.047 f 0.1 f 0.1 f vl 62 100k fw217 3 0.1 f 0.22 f 0.022 f 0.1 f 0.047 f 4700pf 4700pf 4700pf 4700pf 1 f 0.082 f 150pf 8.2k 5% 24k 51k 680k 2% 5% 120pf 2000pf 5% 510k 3k 51k 110 1k 1.8k 1k 1k 1k 1k 1k 100k 180pf 100k 51k 680pf 51k 680pf 51k uh vg cp2 cp1 62 uout 100 ul 0.1 62 wh 62 wout 100 wl vreg + - ld vreg 3k 33k 1m vreg br rst f/r s/s curr comp int osc lvsd edges detect charge pump control amp speed discri speed pll vco fg fil 3-hall mix latch 1/32 1/16 pout ld 1/512 vco pll rc comp csd osc fgs clk
lv8105w no.a1271-8/21 relations hall input with drive output (1) when f/r = ?l? and the soft current-carrying output. in1 in2 in3 (uh) (vh) (wh) 120 degrees current-carrying (ul) (vl) (wl) uh vh wh soft current-carrying ul vl wl pwm control output synchronous rectification output
lv8105w no.a1271-9/21 (2) when f/r = ?h? and the soft current-carrying output. in1 in2 in3 (uh) (vh) (wh) 120 degrees current-carrying (ul) (vl) (wl) uh vh wh soft current-carrying ul vl wl pwm control output synchronous rectification output
lv8105w no.a1271-10/21 (3) when f/r = ?l? and the 120 degrees current-carrying only. (4) when f/r=?h? and the 120 degrees current-carrying only. in1 in2 in3 uh vh wh ul vl wl pwm control output synchronous rectification output in1 in2 in3 uh vh wh ul vl wl pwm control output synchronous rectification output
lv8105w no.a1271-11/21 pin functions pin no. pin name pin function equivalent circuit 1 csd pin to set the operating time of the constraint protection. connect a capacitor between this pin and gnd. this pin combines also functions as the logic circuit block initial reset pin. 1 vreg 500 reset circuit 3 rc pin to set the speed discriminator output amplitude switching circuit. connect a capacitor between this pin and gnd. and connect a resistor between vreg and this pin. vreg 3 1k 4 intout integrating amplifier output pin. vreg 4 105k 5 intin integrating amplifier inverting input pin. vreg 5 500 500 intout 6 500 30k 30k 6 intref integrating amplifier non-inverting input pin. 1/2 vreg potential. connect a capacitor between this pin and gnd. 7 dout speed discriminator output pin. acceleration ? high, deceleration ? low. vreg 7 continued on next page.
lv8105w no.a1271-12/21 continued from preceding page. pin no. pin name pin function equivalent circuit 8 pout speed control pll output pin. outputs the phase comparison result for clk and fg. vreg 8 9 s/s start / stop control pin. low : 0v to 1.0v high : 2.0v to vreg goes high when left open. low for start. the hysteresis width is about 0.27v. 9 vreg 55k 5k 10 clk external clock signal input pin. low : 0v to 1.0v high : 2.0v to vreg goes high when left open. the hysteresis width is about 0.27v. f = 3khz, maximum. 10 vreg 55k 5k 11 f/r forward / reverse control pin. low : 0v to 1.0v high : 2.0v to vreg goes high when left open. low for forward. the hysteresis width is about 0.27v. 11 vreg 55k 5k 12 br brake pin (short braking operation). low : 0v to 1.0v high : 2.0v to vreg goes high when left open. high or open for brake mode operation. the hysteresis width is about 0.27v. 12 vreg 55k 5k continued on next page.
lv8105w no.a1271-13/21 continued from preceding page. pin no. pin name pin function equivalent circuit 13 fgs fg amplifier schmitt output pin. this is an open collector output. 13 vreg 14 ld lock detection output pin. this is an open collector output. goes low when the motor speed is within the speed lock range ( ? 6.25%). 14 vreg 15 fgout fg amplifier output pin. this pin is connected to the fg schmitt comparator circuit internally in the ic. 15 105k vreg fg schmitt comparator 16 fgin - fg amplifier inverting input pin. vreg 16 500 fgout 500 17 500 30k 30k 17 fgin + fg amplifier non-inverting input pin. 1/2 vreg potential. connect a capacitor between this pin and gnd. 18 19 20 21 22 23 in1 - in1 + in2 - in2 + in3 - in3 + hall input pins. the input is seen as a high level input when in + > in - , and as a low level input for the opposite state. if noise on the hall signals is a problem, insert capacitors between the corresponding in + and in - inputs. vreg 19 21 23 22 20 18 continued on next page.
lv8105w no.a1271-14/21 continued from preceding page. pin no. pin name pin function equivalent circuit 24 hb hall bias switch pin. goes off when the s/s pi n is the stop state. v cc 24 25 rfgnd output current detection reference pin. connect to gnd side of the current detection resistor rf. vreg 25 2k 26 rf output current detection pin. connect to the current detection resistor rf. sets the the maximum output current iout to be 0.25/rf. vreg 26 5k 28 31 34 ul vl wl output pins for gate drive of the lower side n channel power fet. vreg 28 31 34 continued on next page.
lv8105w no.a1271-15/21 continued from preceding page. pin no. pin name pin function equivalent circuit 30 33 36 uh vh wh output pins for gate drive of the upper side n channel power fet. vg 30 33 36 100 29 32 35 100 29 32 35 uout vout wout pins to detect the source voltage of the upper side n channel power fet. 38 v cc power supply pin. connect a capacitor between this pin and gnd for stabilization. 39 vg charge pump output pin. connect a capacitor between this pin and v cc . 39 40 v cc 100 400 40 cp2 pin to connect the capacitor for charge pump. connect a capacitor between this pin and cp1. 41 cp1 pin to connect the capacitor for charge pump. connect a capacitor between this pin and cp2. v cc 41 43 vreg 5v constant voltage output pin (5.6v). connect a capacitor between this pin and gnd. 43 v cc continued on next page.
lv8105w no.a1271-16/21 continued from preceding page. pin no. pin name pin function equivalent circuit 44 45 gnd2 gnd1 gnd pins. gnd1 and gnd2 are connected in the ic. 46 c vco oscillation pin. connect a capacitor between this pin and gnd. 46 vreg 500 47 r pin to set the charge/disch arge current of the vco circuit. connect a resistor between this pin and gnd. vreg 47 500 48 fil vco pll output filter pin. vreg 48 500 2 27 37 42 nc no connection pins.
lv8105w no.a1271-17/21 description of lv8105w 1. speed control circuit this ic controls the speed with a combination of the speed discriminator circuit and the pll circuit. therefore, when a motor that has large load variation is used, it is possible to prevent the rotation variation as compared with the speed control method only the speed discriminator. the speed discriminator circuit and the pll circuit outputs an error signal once every one fg period. the fg servo frequency signal (f fg ) is controlled to have the equal frequency with the clock signal (f clk ) which is input through the clk pin. f fg = f clk 2. vco circuit this ic has the vco circuit to generate the reference sign al of the speed discriminator circuit. the reference signal frequency is calculated as follows. f vco = f clk ? 512 f vco : reference signal frequency, f clk : clock signal frequency the components connected to the r, c and fil pins must be connected to the gnd1 pin (pin 45) with a line that is as short as possible to reduce influence of noise. 3. output drive circuit this ic adopts a direct pwm drive method to reduce power loss in the output. an external output transistor is always saturated while the transistor is on and driving force of the motor is adjusted by changing the duty that the output transistor is on. the waveform of th e coil current becomes trapezoidal with the current control and the overlap switching of about 15 degrees. therefore, it is possible to reduce the motor noise and the torque ripple when switching the phase to which power is applied (soft current-carrying). when the 120 degrees current-carrying, the pwm switching is performed on the ul, vl and wl pins only. also, when the soft current-carrying, the pwm switching is performed on any the outputs (the ul, vl, wl, uh, vh and wh pins). the pwm frequency is determined with 64khz (typical) in the ic. when the pwm switching of the upper side output is off, the lower side output is turned on. also, when the pwm switching of the lower side output is off, the upper side output is turned on (synchronous rectification). the off-time of the synchronous rectification is determined in the ic and varies from 1.2 ? s to 3.1 ? s. 4. current limiter circuit the current limiter circuit limits the (peak) current at the value i = v rf /rf (v rf = 0.25v (typical), rf : current detection resistor). the current limitation operation consists of reducing the pwm output on-duty to suppress the current. high accuracy detection can be achieved by connecting the rf and rfgnd pins lines near at the ends of the current detection resistor (rf). 5. speed lock range the speed lock range is less than ? 6.25% of the fixes speed. when the motor sp eed is in the lock range, the ld pin (an open collector output) goes low. if the motor speed goes out of the lock range, the on-duty of the motor drive output is adjusted according to the speed error to control the motor speed to be within the lock range. as for the 120 degrees current-carrying a nd the soft current-carrying, when the motor speed goes out of the lock range, the current-carrying becomes the 120 degrees current-carryin g. when the motor speed is within the lock range, the current-carrying becomes th e soft current-carrying.
lv8105w no.a1271-18/21 6. speed discriminator output amplitude switching circuit by the magnitude relation between the time t that is set by using the capacitor and resistor connected with the rc pin and the clock period which is input through the clk pin, th e output amplitude of the speed discriminator switches as follows. when the clock period is smaller than t vreg-1.0v 0.9v when the clock period is bigger than t vreg-1.7v 1.6v when connect a resistor r between the rc pin and vreg and a capacitor c between the rc pin and gnd, the above time t is calculated as follows. t = 0.91 ? r ? c by the variance of the ic, ?0.91? of the above formula has varied from 0.885 to 0.935. when switching the output amplitude of the speed discriminator by the input voltage to the rc pin is performed, input that voltage to the rc pin through the resistor of 20k ? . the output amplitude of the speed discriminator is switched by the input voltage as follows. low level input (0v to 2v), vreg-1.0v 0.9v high level input (4v to 6v), vreg-1.7v 1.6v when there is no need for the speed discriminator output amplitude switching, connect the rc pin with gnd. in this instance, the high level output voltage of the speed discriminator becomes vrec-1.0v and the low level output voltage of the speed discriminator becomes 0.9v. 7. hall input signal the input amplitude of 100mvp-p or more (differential) is desirable in the hall sensor inputs. the closer the input wave-form is to a square wave, the lower the required input amplitude. inversely, a higher input amplitude is required the closer the input waveform is to a triangular wave. also, note that the input dc voltage must be set to be within the common-mode input voltage range. if a hall sensor ic is used to provide the hall inputs, those signals can be input to one side (either the + or - side) of the hall sensor signal inputs as 0 to vreg level signals if the other side is held fixed at a voltage within the common-mode input voltage range that applies when the hall sensors are used. if noise on the hall inputs is a problem, that noise must be excluded by inserting capacitors across the inputs. those capacitors must be located as clos e as possible to the input pins. when the hall inputs for all three phases are in the same state, all the outputs will be in the off state. the bias of the hall element can be cut by supplying the bias of the hall element from the hb pin while the s/s pin is a stop mode(hall bias switch). the hall input frequency range possible for the soft current-carrying is determined from 30hz to 500hz (in1 frequency). 8. s/s switching circuit when the s/s pin is set to the low level, s/s switching circuit is the start mode. inversely, when the s/s pin is set to the high level or open, s/s switching circuit is the stop mode. at the stop mode, all the outputs will be in the off state. this ic will be in the power save state of decreasing the supply current at the stop mode. 9. braking circuit when the br pin is set to the high level or open, the brake is on. inversely, when the br pin is set to the low level, the brake is released. the brake becomes a short brake that turns on the lower side output transistors for all phases (the ul, vl and wl side) and turns off the upper side output transistors for all phases (the uh, vh and wh side). note that the current limiter does not operate during braking. during braking, the duty is set to 100%, re gardless of the motor speed. the current that flows in the output transistors during br aking is determined by the motor back emf voltage and the coil resistance. applications must be designed so that this current does no t exceed the ratings of the output transistors used. (the higher the motor speed at which braking is applied, the more severe this problem becomes). the braking function can be applied and released with the ic at the start mode. this means that motor startup and stop control can be performed using the br pin with the s/s pin held at the low level (the start mode). if the startup time becomes excessive, it can be reduced by controlling the motor st artup and stop with the br pin rather than with the s/s pin (since the ic will be in the power save state at the stop mode, enough time for the vco circuit to stabilize will be required at the beginning of the motor start operation).
lv8105w no.a1271-19/21 10. forward/reverse switching circuit the motor rotation direction can be switched by using the f/r pin. however, the following notes must be observed if the motor direction is switched while the motor is turning. ? this ic is designed to avoid through currents when sw itching directions. however, increases in the motor supply voltage (due to instantaneous return of the motor current to the power supply) during direction switching may cause problems. the values of the capacitors inserted between power and ground must be in creased if this increase is excessive. ? if the motor current after direction switching exceeds the current limit value, the pwm drive side outputs will be turned off, but the opposite side output will be in the shor t-circuit braking state, and a current determined by the motor back emf voltage and the coil resistance will flow. applications must be designe d so that this current does not exceed the ratings of the output transistors used. (the higher the motor speed at which the direction is switched, the more severe this problem becomes.) 11. constraint protection circuit the lv8105w includes an on-chip constraint protection circuit to protect the motor and the output transistors in motor constraint mode. if the ld output remains high (indicating the unlocked state) for a fixed period in the motor drive state (the s/s pin : start, the br pin : brake release), the lower side output transistors (the ul, vl and wl side) are turned off. this time can be set by adjusting the oscillation frequency of the csd pin by using a external capacitor. by the capacitance of the capacitor attach ed to the csd pin, the set time is calculated as follows. the set time (sec) = 60.8 ? c ( ? f) when a 0.047 ? f capacitor is connected with the csd pi n, the set time becomes about 2.9sec. by the variance of the ic, ?60.8? of the above formula has varied from 40.8 to 80.8. to restart a motor by cancelling the constraint protecti on function, any of the following operation is necessary. ? put the s/s pin into the start state again after the stop state (about 1ms or more). ? put the br pin into the brake release state agai n after the braking state (about 1ms or more). ? turn on the power supply agai n after the turn off state. when the clock disconnect protection function, the thermal shutdown function and the low-voltage protection function are operating, the constraint protec tion function does not operate even if the motor does not rotate. the oscillation waveform of the csd pin is used as the reference signal for some circuits in addition to the motor constraint protection circuit. therefore, it is desirable to oscillate the csd pin even if the constraint protection function is unnecessary. if the constraint prot ection circuit is not used, the oscillati on of the csd pin mu st be stopped by connecting a 220k ? resistor and a 0.01 ? f capacitor in parallel between the csd pin and gnd. however, in that case, the clock disconnection protection circuit will no longer func tion. also, the synchronous rectification does not operate in any of the following cases. ? when the motor does not rotate in the motor constrained state since the motor is started up by the s/s or the br input, the pwm switching is performed by using the current limiter circuit. but, the synchronous rectification does not operate when the oscillation of the csd pin is stopped. the csd pin combines also functions as the initial reset pin. the time that the csd pin voltage is charged to about 1.25v is determined as the initial reset. at the initia l reset, all the outputs will be in the off state. 12. clock disconnection protection circuit if the clock input through the clk pin goes to the no input state in the motor drive state (the s/s pin : start, the br pin : brake release), the lower side output transistors (the ul, vl and wl side) are turned off. if the clock is resupplied, the clock disconnection protection function is cancelled. when the clock period is longer than about thirty-fourth part of the constraint protection set time, the clock disconnection protection circuit judges the clock input to be the no input state and this protection function will operate. 13. thermal shutdown circuit if the junction temperature rises to the sp ecified temperature (tsd) in the motor dr ive state (the s/s pin : start, the br pin : brake release), the lower side output transistors (the ul, vl and wl side) are turned off. if the junction temperature falls to more than the hysteresis width ( ? tsd), the thermal shutdown function is cancelled.
lv8105w no.a1271-20/21 14. low-voltage protection circuit the lv8105w includes a low-voltage protection circuit to protect against incorrect operation when the v cc power is applied or if the power supply voltage falls below its operating level. when the v cc voltage falls under the specified voltage (vlvsd), all the outputs will be in the off state. if the v cc voltage rises to more than the hysteresis width ( ? vlvsd), the low-voltage protection function is cancelled. 15. power supply stabilization since this ic is used in applications that flow the large output current, the power supply line is subject to fluctuations. therefore, capacitors with ca pacitance adequate to stabilize the power su pply voltage must be connected between the v cc pin and gnd. if diodes are inserted in the power supply line to prevent the ic destruction due to reverse power supply connection, since this makes the power supply voltage even more subject to fluctuations, even larger capacitance will be required. 16. ground lines the signal system gnd and the output system gnd must be se parated, and connected to one gnd at the connector. as the large current flows to the output system gnd, this gnd line must be made as short as possible. output system gnd : gnd for rf and v cc line capacitors signal system gnd : gnd for the ic and external components 17. integrating amplifier the integrating amplifier integrates the speed error pulses and phase error pulses and converts them to the speed command voltage. at that time it also sets the control loop gain and the frequency characteristics. external components of the integrating amplifier must be placed as close to the ic as possible to reduce influence of noise. 18. fg amplifier the fg amplifier normally makes up a filter amplifier to rej ect noise. since a clamp circuit has been added at the fg amplifier output, the output amplitude is clamped at abou t 3.2vp-p, even if the amplifier gain is increased. after the fg amplifier, the schmitt comparator on one si de hysteresis(200mv (typical)) is inserted. the schmitt comparator output (fgs output) becomes high level when the fg amplifier output is lower than the fgin + voltage, and becomes low level when the fg amplifier output is higher to more than schmitt width as compared with the fgin + voltage. therefore, it is desirable that the amplifier gain be se t so that the output amplitude is over 1.0vp-p at the lowest controlled speed to be used. the capacitor connect ed between the fgin + pin and gnd is required for bias voltage stabilization. this capacitor must be connected to the gnd1 pin (pin 45) with a line th at is as short as possible to reduce influence of noise. as the fg amplifier and the fgs output ar e operating even if the s/s pin is the stop state, it is possible to monitor the motor rotation by the fgs output.
lv8105w ps no.a1271-21/21 ordering information device package shipping (qty / packing) lv8105w-mpb-e sqfp48(7x7) (pb-free) 50 / tray foam LV8105W-TLM-E sqfp48(7x7) (pb-free) 1000 / tape & reel on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidiaries in the united st ates and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a lis ting of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf . scillc reserves the right to make changes with out further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any parti cular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specific ations can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated fo r each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc pro ducts are not designed, intended, or authorized for use as com ponents in systems int ended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees ar ising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that sci llc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject t oall applicable copyright laws and is not for resale in any manner.

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